# (note: the in the command line is necessary for make to work)Ī simple example of the makefile is shown below. So a generic makefile is as shown below: # comment We can also have a set of target entries for executing a set of commands specified by the target label. o or other executable files in C or C++ and. Now let’s see the general structure of makefile.Ī makefile typically starts with variable declarations followed by a set of target entries for building specific targets. A makefile also contains information like source-level dependencies for each file as well as the build-order dependencies. %make clean #here clean is a target_label specified for rm commands C++ MakefileĪ makefile is nothing but a text file that is used or referenced by the ‘make’ command to build the targets.

The general syntax of make is: %make target_label #target_label is a specific target in makefileįor example, if we want to execute rm commands to clean up files, we write: The make command is used in the makefile to build modules or to clean up the files.

The make tool reads all these rules and behaves accordingly.įor example, if a rule specifies any dependency, then the make tool will include that dependency for compilation purposes. There are various rules that are specified as target entries in the makefile. Make is a UNIX tool and is used as a tool to simplify building executable from different modules of a project.

Makefile for c program